The present invention relates to a LSI semiconductor memory device, and particularly to a socalled dynamic random access memory device (referred to as a dynamic RAM hereinafter).
FIG. 1 shows a typical arrangement of a dynamic RAM, in which MCA depicts memory cell arrays, WL word lines, BL bit lines, and SA sense amplifiers. The numbers of the word lines WL and the bit lines BL in each memory cell array MCA depend upon its memory capacity. For clarity of illustration, only a single word line and a single bit line are shown in FIG. 1.
FIG. 2 shows one of the memory cells in the memory cell array MCA in FIG. 1. Such a memory cell is known for example, from Japanese Laid-Open Patent Application No. 58295/1982. In FIG. 2, reference numeral 1 depicts a diffusion layer, 2 a cell plate formed by a first polycrystalline silicon layer, 3 a transfer gate formed by a second polycrystalline silicon layer, BL a bit line made of aluminum, and C a contact connecting the diffusion layer and the bit line. The diffusion layer 1 and the cell plate 2 form a capacitor for the memory cell. The transfer gate 3 functions as the word line in FIG. 1.
FIG. 3 shows the bit line BL and the contacts C in an edge portion of the memory cell array MCA, which is defined by points a, b, c and d in FIG. 2, and aluminum wiring outside the memory cell array. In FIG. 3, BL1, BL1 and BL2 are bit lines, and C11a, C11b, . . . , C21b are contacts connecting the diffusion layer and the bit lines. Reference numeral 4 depicts aluminum wiring which short-circuits the cell plates 2 in FIG. 2 in the edge area of the memory cell array MCA in FIG. 1, and C4a to C4c are contacts connecting the cell plate 2 and the aluminum wiring 4.
In the conventional dynamic RAM shown in FIG. 3, the distance d2 between adjacent bit lines and the distance d1 between the bit line and the bit line of the contact portion are commonly set for every bit line, and the distance d4 between the outermost bit line BL1 and the aluminum wiring 4 disposed outside the outermost bit line BL1 and the distance d3 between the aluminum wiring 4 and the outermost bit line BL1 of the contact portion are set differently from the distances d1 and d2. In the illustrated case, d3 and d4 are smaller than d1 and d2, respectively.
The sense amplifier SA is arranged outside the memory cell array MCA, as shown in FIG. 1. FIG. 4 shows the connections between the bit lines BL1 and BL1 and a sense amplifier SA composed of insulated gate type n-channel field effect transistors (FETs) QS1 and QS2.
The bit lines BL1 and BL1 are connected to the drains of the FETs QS1 and QS2, respectively, to the gates of which the bit lines BL1 and BL1 are connected, respectively. The sources of the FETs are connected commonly to receive a sense amplifier activating signal S. WL1 and WL2 are word lines and DWL1 and DWL2 are dummy word lines. QC1, QC2 and CC1, CC2 are FETs and capacitors, respectively, which constitute the memory cell. QR1 and QR2, which are FETs used for discharging the dummy cells, have gates connected to receive a dummy cell reset signal RST.
To the bit lines BL1 and BL1, stray capacitors CS10 and CS20 with respect to ground potential and an interline capacitor CS12 between the bit lines BL1 and BL1 are connected. An interline capacitor CS14 is formed between the outside aluminum wiring 4 and the bit line BL1, and an interline capacitor CS23 is formed between the bit line BL1 and the adjacent bit line BL2. Since the configurations of the bit lines BL1 and BL1 are similar, the capacitors CS10 and CS20 have substantially the same capacitance. Further, since the distances d1 and d2 between the adjacent bit lines are different from the distances d3 and d4 between the outermost bit line BL1 of the memory cell and the aluminum wiring 4, the capacitors CS23 and CS14 have different values, namely, CS23&lt;CS14. Therefore, the total capacitance connected to the bit line BL1 is larger than that connected to the bit line BL1.
The operation of this dynamic RAM will be described with reference to a case where the content of the capacitor CC1 of the memory cell in FIG. 4 is read out under the assumption that the content is "1". Operational waveforms of the bit lines are shown in FIGS. 5A and 5B.
Under the stated conditions, the dummy cell reset signal RST is set to the "H" (high) level, causing the FETs QR1 and QR2 to be turned on and the capacitors CD1 and CD2 to be discharged. Further, the bit lines BL1 and BL1 are precharged to "H" levels by suitable precharge circuitry (not shown). Then, after the dummy cell reset signal RST becomes "L", the word line WL1 and the dummy word-line DWL2 are set to "H" levels at a time instant t.sub.0, causing the FETs QC1 and QD2 to be turned on and thus connecting the capacitors CC1 and CD2 to the bit lines BL1 and BL1, respectively. It is to be noted that charges on the stray capacitor CS10, those on the interline capacitors CS14 and CS12, and those on the capacitor CC1 are averaged on the bit line BL1, and charges on the stray capacitor CS20, those on the interline capacitors CS23 and CS12, and those on the capacitor CD2 are averaged on the bit line BL1.
Since the capacitance of the capacitor CC1 of the memory cell is larger than that of the dummy cell capacitor CD2, assuming as above that the memory content of the capacitor CC1 is "1", when the dummy cell capacitor CD2 is discharged (placed in the "0" state), the potential of the bit line BL1 will rise above that of the bit line BL1. At this time, since the total capacitance of the capacitors connected to the bit line BL1 is larger than the total capacitance of the capacitors connected to the bit line BL1, the potential of the bit line BL1 (precharged to the "H" level) is hardly varied.
Then, when the sense amplifier drive signal S becomes "L" at a time instant t.sub.1 and the sense amplifier is activated, the FETs QS2 and QS1 are turned on and off, respectively, since the potential of the bit line BL1, i.e., the gate potential of the FET QS2, is higher than the potential of the bit line BL1, i.e., the gate potential of the FET QS1, as shown in FIG. 5A, causing the potential of the bit line BL1 to be further lowered. Thus, the memory content "1" of the memory cell capacitor CC1 is read out on the bit line BL1.
A reading out operation of a memory content of "0" of the capacitor CC1 will be described. In this case, the discharge of the dummy cell capacitor, the precharging of the bit line, and the operations of setting the word line and the dummy word line to "H" levels are the same as those described previously.
When the capacitors CC1 and CD2 are connected to the bit lines BL1 and BL1, respectively, the potentials of the bit lines BL1 and BL1 are both lowered since the memory content of the capacitor CC1 is "0", and the capacitor CD2 has been discharged (set to the "0" state).
As mentioned previously, the cpaacitance of the capacitor CC1 is larger than that of the capacitor CD2, and the capacitors CS14 and CS23 connected to the respective bit lines BL1 and BL1 satisfy the relation CS14&gt;CS23. If the difference between the capacitances of CS14 and CS23 is large, the potential of the bit line BL1, as shown in FIG. 5B, will fail to fall below that of the bit line BL1, and thus the FETs QS2 and QS1 are turned on and off, respectively. Therefore, the potential of the bit line BL1 does not follow the dotted line in FIG. 5B, and the potential of the bit line BL1 is further lowered. As a result, the memory content is read out on the bit line BL1 as a "1", causing an erroneous reading.
Thus, in the conventional semiconductor memory device, erroneous read out is unavoidable for the outermost bit line since the distance between the adjacent bit lines is different from the distance between the outermost bit line and the aluminum wiring outside the latter bit line; that is, the capacitance between the adjacent bit lines is different from the capacitance between the outermost bit line and the wiring, even if the arrangement of bit lines in the memory cell array is symmetrical.
Particularly, in the case where the distance between the outermost bit line and the aluminum wiring is smaller than that between the adjacent bit lines, read-out error tends to occur when the capacitor connected to the outermost bit line stores a "0". On the other hand, in the case where the distance between the outermost bit line and the wiring is larger than that between the adjacent bit lines, read-out error tends to occur when the capacitor connected to the outermost bit line stores a "1" since the capacitance connected to the outermost bit line is smaller than that connected to the other bit lines.
This defect becomes more pronounced as the integration density increases due to the decreased distance between adjacent bit lines. That is, with a decrease of the inter-bit line distance, the inter-bit line capacitance is increased with respect to the total bit line capacitance, and when there is an unbalance in the inter-bit line capacitance as mentioned previously, normal read-out operations of the dynamic RAM are impossible.